Fundamentals of CMOS VLSI

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CMOS VLSI 1-2008

Part A

1. Write neat diagrams and explain the working of the nMOS Enhancement type transistor.                                                       

2. Give the MOS device design equations in detail. (10 marks)

Part B

3. Explain in detail the working of a Transmission gate in 
detail.                                                                          (10 marks)

4. What is the significance of the Lambda based design rules.  (10 marks)

Part C

5. Draw the stick diagram for the CMOS Nand gate .  5 marks)  

6. Draw the symbolic diagram of CMOS inverter.   (5 marks)

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CMOS VLSI 2-2008

Part A

1 (a) Explain the features of pseudo nMOS logic with an
       example                                                                      (04 marks)

   (b) With XNOR truth table design pass transistor logic.

         What are it’s  advantages and disadvantages?           (06 marks)

2 (a) What is dynamic CMOS Logic? Explain the “precharge” and  

        “evaluate” of this logic.                                             (06 marks)

   (b) With an example and circuit diagram explain features of

         C²MOS logic.                                                     (04 marks)

Part B

3 (a) Draw BiCMOS Nand gate with NPN pull down and bring

         out it’s features.                                                  (06 marks)

   (b) With an example bring out the features of CMOS

         complementary logic.                                 (04 marks)

4 (a) Write the stick diagram for two input CMOS NOR gate.        (06 marks)

   (b) Explain the disadvantages of two inputs NMOS NAND gate (04 marks)

Part C

5. Briefly explain the architectural issues of subsystem design       (05 marks)

6. Derive the overall ratio of two input NAND gate using NMOS

    and show that it is 4:1.                                               (05 marks).

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CMOS VLSI 3-2008

Part A

1. What is a parity generator? Draw the basic one-bit cell of parity generator with stick diagrams for nMOS. Also write the equations for the conditions                                                                               (10 marks)

2. (a) Explain the active passive and precharged bus concepts with neat diagrams                                                                                 (06 marks)

(b) A MOS layer is 5 λ wide, 60 λ long and 1 µm thick. The resistivity of the layer is 1 Ω cm. Using sheet resistance concept, calculate the resistance of the MOS layer along its length. Derive the equations used in the calculations.                                                                                                                                                                                     (04 marks)

Part B

3. Write the basic digital processor architecture. Explain the one bus, two bus and three bus architecture with diagram for basic ALU structure

                                                                                                          (10 marks)

4. Explain how large capacitive loads are driven using cascaded inverters.

                                                                                                         (10 marks)

Part C

5. What are the disadvantages of 4x4 cross bar switch used as a shifter? Draw the circuit which overcomes these disadvantages and explain.

                                                                                                        (05 marks)

6. Explain the working of super buffers. Draw the inverting and non-inverting type of super buffers.                                                   (05 marks)

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